# PCIe 1805 AI, Measurements out of uncertainty **URL:** \ **Category:** Hardware\ **Created:** [October 6, 2026, 8:41am UTC](https://forum.aim-linux.advantech.com/t/pcie-1805-ai-measurements-out-of-uncertainty/1532 "2026-10-06T08:41:38Z")\ **Posts on this page:** 1\ **Page:** 1
**Author:** ![leo7](https://avatars.discourse-cdn.com/v4/letter/l/13edae/32.png) [@leo7](https://forum.aim-linux.advantech.com/u/leo7)\ **Post date:** [October 6, 2026, 8:41am UTC](https://forum.aim-linux.advantech.com/t/pcie-1805-ai-measurements-out-of-uncertainty/1532/1 "2026-10-06T08:41:38Z")
Hello, I have two boards PCIE-1805, I noticed that there is an offset in the measurement using Navigator and I believe that it comes from the boards. Therefore, I would like to know if It’s a known Issue / If it could be a malfunction of the boards. I generate a voltage signal 9,9V using an AOIP CALYS 1500 with the 10V range. The signal is transmitted directly to 1805 using an ADAM-3962, a DB-62 cable and Test Leads with Banana Plugs. I have a multimeter in parallel to see if the CALYS generate the right signal and it does. I measured in differential, with channel 0&1, 2&3, 4&5, 6&7, 8&9, 10&11. Here are the measurements I have with the 1805 channel 10&11, which has the worst measurement: 9,89221 9,88921 9,89277 9,89333 9,88996 9,88902 9,89315 9,89005 9,88827 9,8938 Average = 9,891177, We can clearly see an offset of 0,008823 V. I have calculated the uncertainty of the complete measurement chain. I have U = 6 mV (K=3) with the following elements. Unoise = 0,1mV gain error = ±0,03 % Offset error = ±1,5 mV 16 bit resolution on ±10V scale, LSB = 0,305 mV Usource Calys = 0,78 mV Let me know if It is coherent for you. My measurements are clearly out of uncertainty. My DC source is up to date. I tested to change the ADAM-3962 and DB-62 cable, nothing changed. I did the auto-calibration of the boards, nothing changed. I have the same result with the second board.